The present invention relates to a method for making semiconductor devices.
Dual damascene metal interconnects may enable reliable low cost production of semiconductor devices using sub 0.25 micron process technology. Unlike conventional processes, which only require patterning of vias, processes for making dual damascene structures also require patterning of trenches that will be etched into a dielectric layer. That dielectric layer lies on top of various other layers, which may be made of metal or other materials. Those layers"" varying thicknesses impart varying optical properties to the structure. As a result, when light strikes the surface, it may be reflected in a non-uniform and uncontrollable fashion. Such non-uniformity may cause the critical dimension (xe2x80x9cCDxe2x80x9d) control across a wafer to be poor.
In addition to that substrate reflectivity problem, when the trench is formed within the dielectric layer (e.g., a silicon dioxide layer), an etch chemistry must be used that has a very high selectivity for that dielectric layer over an underlying protective layer (e.g., a silicon nitride layer). Such high selectivity is required to ensure that the protective layer prevents an underlying copper layer from being exposed to processes used to etch the trench. Unfortunately, using an etch chemistry that provides such high selectivity may adversely affect the quality of the via and trench profiles that result from the etch process.
A process has been proposed to address these issues. In that process, the via is filled with a sacrificial material prior to etching the trench. Filling the via with that material enables the trench to be etched using an etch chemistry that ensures high quality via and trench profiles, without having to consider the relative selectivity between the dielectric layer and the protective layer. That sacrificial material may be dyed or covered with an appropriate antireflective coating to produce a light absorbing background that ensures uniform reflectivity of light used to expose the photoresist during trench patterning. Examples of this process are described in copending applications Ser. Nos. 09/422,821 and 09/501,354 (filed Oct. 21, 1999 and Feb. 9, 2000, respectively, and each assigned to this application""s assignee).
Although that proposed process addresses selectivity and substrate reflectivity problems, it raises a new one. Conventional photoresist ashing and trench clean processes may not adequately remove the sacrificial material used to fill the via. Accordingly, there is a need for an improved process for cleaning vias and trenches that have been etched into a dielectric layer. There is a need for such a process that allows a via to be filled with a sacrificial material prior to etching the trench, and then removed after the trench is etched. There is a need for such a process that is both manufacturable and capable of providing high yields. The post etch clean sequence of the present invention provides such a process.